Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling.

By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and enables smaller, thinner packages with faster memory/processor speeds — and all of this while consuming less power.

Process tools for hybrid bonding must meet critical process specs, such as incredibly flat 300mm wafer polishing (<1nm center-to-edge non-uniformity), zero particles on bonded wafers, 100nm die placement accuracy, among other things.

A humble beginning
Hybrid bonding made its debut more than a decade ago in CMOS image sensors, which dissociated the pixel array chip from the logic chip to maximize the area for backside illumination. That was followed by 3D NAND companies, which began using wafer-to-wafer hybrid bonding because of the limitation on deep and narrow trench etching in NAND arrays that now require multiple tiers. AMD was the first to stack SRAM on core logic using hybrid bonding for chiplet-based CPUs.

Now the industry is working to adopt hybrid bonding for high-bandwidth memory (HBM) stacks of 8, 16, or more DRAMs. This is an uphill battle, as lower thermal budget processes are needed to prevent DRAM refresh degradation. HBM calls for lower deposition temperatures and annealing below the current 300 to 350°C range. The latest developments include:

  • Lower temperature deposition processes for SiCN with high bonding energy;
  • CMP processes that control topography within 1nm;
  • Nanocrystalline copper plating with (111) orientation that bonds at 200°C;
  • Wafer dicing by laser and/or plasma dicing; and
  • Die-to-wafer bonders with high parallelism and <200nm accuracy.

The thermal budget is the overriding concern when it comes to high bandwidth memory (HBM) stacks. “By replacing the solder inside the HBM with copper-to-copper connections, one can expect a much finer pitch, thinner bond line thickness (BLT), and more robust joints,” said Wei Zhou, packaging R&D lead at Micron. [1] He explained that wafer-to-wafer bonding, where identical chip sizes on each wafer are needed, currently dominates because of the simpler wafer handling and better process defect control. Die-to-wafer hybrid bonding requires a carrier wafer and organic glue layer, which typically limits thermal budget to 250°C or lower.

Intel recently announced a new chip architecture and process changes for extending hybrid bonding capability from a pitch of 9µm to 3µm. This entails adjusting the dielectric stack to improve reliability with closer pitch and spacing between pads; reducing bonding layer thickness to enable some pad metal protrusion during annealing; and new CMP recipe and slurry to enable low copper dishing and a smooth dielectric surface. [2] Adel Elsherbini, senior principal engineer at Intel’s Components Research, and his colleagues emphasized three assembly process optimizations for cleanliness, testing, and high placement accuracy. First, dies on two wafers are tested with high test coverage (>99%) to minimize the chance of a latent defect causing a multi-chip system to fail. The size, shape, and contrast of fiducial marks are designed into the layer. Then, the CMP, dicing and surface cleaning are optimized for good alignment and throughput. The accuracy of the die placement system depends on such factors as active thermal control, controlling vibration, and controlling particulate levels.

How the process works
The process flow for hybrid bonding starts out similar to on-chip damascene processes, where cavities are etched into the bonding dielectric, then filled with barrier metal, seed, and copper ECD. The CMP process that follows is optimized for high across-wafer uniformity to produce as smooth a dielectric surface as possible (RMS roughness of 0.2nm is ideal), while achieving a few nanometers of dishing in the copper (which fills upon annealing) regardless of interconnect pattern density.

Next, a dielectric activation step uses a plasma to generate dangling Si-O bonds followed by DI rinse to hydrate the dielectric. Next, the KGDs from wafer 2 are aligned with and bonded to wafer 1, the wafer pair are annealed at 350°C for 2 hours, then the topside silicon wafer undergoes edge processing and is ground down to its final thickness using silicon CMP. The assembly process may then continue with RDL, or the wafer is available for bonding to another wafer with KGD.

Fig. 1: The die-to-wafer hybrid bonding extends to 1μm and wafer-to-wafer hybrid bonding extends to 0.5 μm (500nm) pitch. Source: imec

Hybrid bonding refers to the simultaneous bonding of dielectric and metal bond pads in one bonding step. There are two flavors of hybrid bonding. One is wafer-to-wafer bonding, which is more mature, but limits the combination to same die sizes. The second is die-to-wafer bonding, which involves many more process steps and individual placement of dies on a carrier wafer or glass (collective die-to-wafer approach). In both cases, two wafers that have been processed up through BEOL metallization undergo CVD of the bonding dielectric, damascene deposition of barrier then copper fill, planarization of dielectric with slight copper recess, plasma activation to prepare for bonding, alignment, bonding at room temperature, and annealing to make electrical connection of copper pads. From there it proceeds to back-grinding of the silicon wafer to final thickness (typically <100nm), singulation, and on to final assembly and packaging.

There are four likely candidates for bonding dielectric — silicon dioxide, silicon carbon nitride (SiCN), silicon oxynitride (SiON). Of those, SiCN has emerged as a leading choice because of its high bonding energy, good moisture resistance, and superior barrier properties to copper diffusion. SiCN has been proven able to maintain the hydrophilic behavior for longer periods of time, and the TEOS and the Ar/N2 PECVD process can be tuned for a precise Si:C:N ratio that maximizes bonding strength. Applied Materials, Lam Research and SPTS KLA are manufacturers of PECVD systems.

Imec and SPTS KLA recently developed a PECVD deposition process at 175°C that exhibits good bonding behavior following a 200°C densification step. [4] In reliability studies, the researchers determined the LT-SiCN outperformed the standard PECVD SiCN film with substantially longer TDDB (time-dependent dielectric breakdown) behavior for a 25µm film. The ideal film contained relatively higher nitrogen content and lower carbon content than the standard SiCN process.

The copper deposition is similar to the damascene copper module for BEOL metallization. Barrier metal, and then copper seed layer, are deposited on the dielectric sidewalls followed by copper electrochemical deposition (ECD). A nano-twinned copper process developed by Lam Research is able to achieve a fine-grained continuous structure after annealing.

Die-to-wafer bonding challenges
An important layer in die-to-wafer bonding is the temporary bonding material that adheres the bottom die to the silicon wafer or glass wafer carrier.

“The temporary bonding material has a little give in it so that it can accommodate chiplets with slightly different thicknesses,” said Rama Puligadda, CTO of Brewer Science. She emphasized that the temporary bonding and release layer must have the thermal budget for all the processes of hybrid bonding or thermocompression bonding, as the case may be, then be released cleanly without residue or particles after bonding. “The temporary bonding material must be compatible with the various chemistries and high-temperature processes — as well as RDL or molding, for instance — without any die shift.” Debonding can be performed using a mechanical blade, laser, or newer pulsed UV light release.

Micron’s Zhou and colleagues determined that by replacing the organic glue it was using for temporary bonding with an inorganic film, higher thermal budgets were allowed, particulate levels were lower, and the CMP process achieved greater uniformity of copper dishing. Approximately 3 to 5nm of dishing in the planarized copper pads is needed, because copper expands relative to the dielectric during annealing.

The copper/dielectric CMP step is one of the most critical steps in the flow. It determines the flatness of the surface to be bonded (<1nm/µm roll-off is allowed). The dielectric should have a completely smooth surface (<2Å RMS roughness). Most importantly, the copper must have uniform recess levels on all copper pads.

The plasma surface activation step works to create several dangling Si-O sites that will enable high bonding strength (>2.0 J/m2) without oxidizing the copper pads or sputtering copper onto other parts of the film or the walls of the process chamber. Samsung Electronics recently showed that a nitrogen plasma activation step, at a pressure almost 2X that of the oxygen reference plasma process, created good process conditions for SiCN films with copper pads ranging from 0.4 to 0.7µm per side (square pads). [3] The Samsung engineers used a reactive molecular dynamics simulation to determine the Ar/N2 plasma gas flows and bias power in the capacitively coupled rf reactor needed to deliver a SiCN surface that is most susceptible to bonding while minimizing copper re-sputtering.

After activation, wafers are rinsed in DI water, followed by alignment of top and bottom wafers and bonded at room temperature. Bonding strength is measured using the Maszara blade test technique. Scanning acoustic tomography is utilized to scan the bonded interface for voids, which appear as white dots on SAT images.

After bonding, the bonded wafer edges are trimmed and the top silicon wafer is ground down using silicon CMP. Wafer-edge defectivity must be tightly controlled during this CMP process.

“After wafers are bonded, a typical process is to edge trim the bonded wafer topside before grinding the top silicon substrate. It is often difficult to precisely control edge trim depth to stop at the bonding interface. After top silicon wafer partial grinding, reactive ion etching (RIE) is often used to remove the remaining silicon,” explained Kai Ma, engineering manager at Applied Materials. “If edge trim goes into the bottom wafer during RIE, etchant would create an undercut into the bottom wafer. This is because the etch-stopping dielectric layer was removed at the wafer edge during the edge trim process. If edge trim stops before reaching the bonding interface, and a Si RIE process is applied to remove post-grinding remaining silicon, then dangling membranes can form at the wafer edge bevel area, eventually becoming flake defects.” [5] The engineers found that by limiting the edge trim depth to a few microns above the bonding interface, they could remove the remaining silicon and bevel membranes, resulting in minimized edge defects.

Finally bonded chips are singulated using blade dicing, laser (stealth) dicing or plasma dicing methods. Because the top dies wafers are diced prior to placement and bonding, the singulation method must be contaminant free. “The mitigation of dicing-induced particles is obviously significant to the success of this technology. The chip-to-wafer stacking process is run in a sequential mode, which means it will take hours to complete just one memory wafer stacking,” said Zhou. In addition, even small particles can grow to create a 20X larger void at the bonding interface that prevent bonding. The Micron group decided to use laser dicing to first carve through multiple dielectric films on the streets followed by plasma dicing of the silicon bulk.

Another method engineers use to address particulate generation during processing is to deposit a protective layer, such as photoresist or other material, which is removed before the next process step.

The processes for hybrid bonding — including dielectric PECVD, copper ECD, CMP, plasma activation, alignment and bonding, and singulation — all involve stringent specifications for film quality, high levels of cleanliness and the assurance of known good die with high test coverage. While the industry is making great strides on integrating these processes, it will continue to pursue lower-temperature alternatives so that sensitive memories like HBM eventually can take advantage of hybrid bonding technology.

1. V. S. Kumar Channam et al., “Low temperature SiCN as dielectric for hybrid bonding,” 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3, doi: 10.1109/EDTM55494.2023.10103036.
2. A. Elsherbini et al., “Enabling Next Generation 3D Heterogeneous Integration Architectures on Intel Process,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 27.3.1-27.3.4, doi: 10.1109/IEDM45625.2022.10019499.
3. S. H. Hahn et al., “Contamination-Free Cu/SiCN Hybrid Bonding Process Development for Sub- μm Pitch Devices with Enhanced Bonding Characteristics,” 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1390-1396, doi: 10.1109/ECTC51909.2023.00238.
4. V. S. Kumar Channam et al., “Low temperature SiCN as dielectric for hybrid bonding,” 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3, doi: 10.1109/EDTM55494.2023.10103036.
5. K. Ma et al., “0.5 ¼m Pitch Wafer-to-wafer Hybrid Bonding with SiCN Bonding Interface for Advanced Memory,” 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1110-1114, doi: 10.1109/ECTC51909.2023.00190.

Related Story

Hybrid Bonding Moves Into The Fast Lane

Source: https://semiengineering.com/gearing-up-for-hybrid-bonding/