What’s different from other RISC-V designs and what’s needed to ensure it works as planned.


Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and compare environment. Larry Lapides, vice president at Imperas, talks about the need to verify asynchronous events like interrupts, how to compare a reference model to RTL, and the need for both hardware/software co-design and architectural analysis.

Ed Sperling

Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Source: https://semiengineering.com/verifying-a-risc-v-processor-model/