What factors can impact time-to-market for advanced nodes and packages.
Increasing complexity and smaller process nodes make it far more difficult to achieve design closure for chips. There are more physical effects to model, including noise, cross-talk, and double switching effects, all of which can slow the design process. Solaiman Rahim, vice president of engineering for Synopsys’ EDA Group, talks about why it’s so important to analyze violations in design, how ECOs can impact closure, and how to get beyond the “last mile” of design issues.
Ed Sperling is the editor in chief of Semiconductor Engineering.