The massive proliferation of semiconductors in more markets, and more applications within those markets, is expected to propel the industry to more than $1 trillion by 2030. But over the next 17 years, semiconductors will reach well beyond the numbers, changing the way people work, how they communicate, and how they measure and monitor their health and well-being.
Chips will be the enabling engines, requiring massive investments in new technology, materials, and manufacturing processes, from the leading-nodes to mature processes that can be leveraged in new ways. But how to continue building them will require substantive changes across every manufacturing and packaging process. In general, those innovations fall into four distinct areas:
- Making patterning more cost effective;
- Faster interconnects through new materials and hybrid bonding;
- Better modeling to simulate processes and systems before running test wafers, and
- Efficient integration of disparate chip functions for smaller, cheaper faster electronics.
Scaling is just one piece of that puzzle, but a critical one. “If you look at the roadmaps of TSMC, Intel, Samsung supported by IBM, and imec, they’re all very much proponents of Moore’s Law, with two-year progressions from 5nm to 3nm to 2nm. From the standpoint of per-unit volume rather than unit area, you can make the argument that, yes, we’re still on Moore’s Law,” said Dean Freeman, semiconductor content specialist of Kiterocket. “There’s a lot of runway left, probably through 1nm.”
That runway will be needed, too. AI and machine learning, which is showing up in everything from smart door locks to assisted driving in cars, has created an insatiable appetite for compute power. “With the increasing complexity of training models, with billions to trillions of parameters, the compute needs are doubling every 3.5 months — much faster than Moore’s Law,” said Sri Samavedam, senior vice president of CMOS technologies at imec.
Processing all of this data is only part of the compute picture. Also needed are denser and more tightly integrated memory, logic, RF, power semiconductors, and sensors for automotive, compute and data storage, and wireless. Collectively, those technologies account for 70% of all industry growth through 2030, according to McKinsey.
And all of that requires more data throughput, which in turn requires faster throughput between chips. Hybrid bonding, already in production using wafer-to-wafer bonding for image sensors — and soon to be implemented in flash memory and HBM — will be critical for enabling these heterogenous combinations. It also may spawn new options for more powerful but more cost-effective solutions. “With SRAM scaling slowing down dramatically, it does not make sense to build large caches in the most advanced node,” said Samavedam. In this case, fabrication of SRAM at an established node, and bonding it to a leading-edge processor using die-to-wafer hybrid bonding, may prove most cost-effective.
This trend to smarter, more-efficient computing also is changing the way fabs and process tools operate. In effect, the machines that make the machines need to become smarter. “Increasingly, data has also become a critical asset during the manufacturing process,” said Barrett Finch, senior director of product marketing at Lam Research. “One example is our data analysis platform, which brings together data intelligence with advanced plasma etch capabilities to deliver advanced uniformity and etch profile control to maximize yield and lower wafer costs.”
Equipment companies are also innovating in response to particular market segments. For instance, in 3D NAND flash, the number of layers continues to grow and necessitates the adoption of multiple stacked tiers in the future, eventually creating vertical strings of stacked devices. These demands require continual improvement, from etching processes to process structures with smaller dimensions and higher aspect ratios.
“Of course, patterning is also becoming exponentially more difficult, especially when it comes to alignment from tier to tier and string to string due to the stresses and higher-order distortions created by the multi-layer stacks,” said Robert Clark, senior member of the technical staff and technology director of TEL.
In addition, the way the industry operates has changed. Whereas chipmakers once made different chips at a range of nodes and marketed them, now the whole electronic ecosystem needs to work together to produce systems. “To integrate heterogenous chiplets in a common package, we are ensuring that everything from material selection to design to device architecture, integration, and packaging are all optimized for the final end-application – what we call the full-stack approach. It means multiple players in the ecosystem have to work together,” said Raj Jammy, chief technologist at MITRE Engenuity and executive director of the Semiconductor Alliance.
But the most dramatic shift is happening as a result of advanced packaging approaches functioning as the primary driver of device performance. Though this trend began decades ago with breakthroughs in TSVs and flip-chip packaging, multi-chiplet packages are starting to move from high-end applications to more mainstream applications.
While TSMC, Samsung and Intel continue their pursuits of 3nm, 2nm, and on to 1.x nm technology nodes, several technology transitions will occur at the transistor and package levels in mainstream fabs and assembly lines, and with the incorporation of new materials, processes, and data analytics to meet all roadmaps.
“For future applications that require high voltages and temperatures, we will need to move beyond silicon to wide-bandgap devices, which have already made headway in EV, industrial, and consumer applications,” said Steven Hsu, vice president of technology development at UMC.
A slew of new materials are in research, with some beginning to move to production. “Looking at some of the leading-edge logic and memory manufacturers, we’re expect to see new materials enter high-volume manufacturing in the next five years or so, like molybdenum for interconnects,” said Dan Tracy, director and senior market analyst at Techcet. “Work needs to happen on precursors to deposit that, or ruthenium, and tool companies need to develop the CMP and cleaning processes for these new chemistries.”
The key driver of assembly and test platforms is RF front-end modules for consumer and mobile products, power packages for electric vehicles, and co-packaged optics, because of the power budget of data servers, according to Curt Zwenger, vice president of advanced SiP product development at Amkor. “Co-packaged optics reduces the length of the electrical interface between the optical engine and the ASIC switch to only a few millimeters. Additionally, this addresses the need for energy reduction and cuts the latency associated with extracting the clock and data from the electrical signal.”
The lithography cell, with its supporting infrastructure of photoresist tracks and metrology tools, is the focal point of the fab. Once wafers are patterned, they progress to the next step (deposition, etch, ion implantation, etc.), but then return to lithography to pattern the next mask level, a process that repeats until the wafers leave the fab.
Patterning with extreme ultra-violet (EUV) scanners has only begun in production. “The cost of lithography just got even more astronomical, so everyone’s having to get more creative and how they define and design their products,” said Brian Wilbur, director of product service diversification at Brewer Science. “Customers have had limited time working with the tools, so they rely on initial evaluations that were performed at ASML or at imec, and they’re just now starting to play with the EUV process to determine where the failure modes are and what the next revision of materials should look like.”
One of the key failure modes is stochastic defects. “Stochastics, which is talked about a lot, is becoming even more of a yield driver, so you have to get everything else right in terms of process targeting by layer, by customer or both. Process integration is much more challenging for both the customer as well as the suppliers to have a product that actually can deliver the absolute best results possible at that particular layer.”
Fractilia recently introduced a tool that runs alongside CD-SEMs to help quantify and control stochastics in high volume manufacturing. “It’s our understanding that stochastic variations are the leading cause of yield loss at 3 and 2nm nodes,” said Chris Mack, CTO of Fractilia. Stochastic variations show up as feature roughness, local CD errors, global CD errors (across wafer), or overlay errors. The tool provides real-time detection of these variations to provide feedback to the patterning process.
Suppliers like Brewer Science are performing more characterization work up-front to enable increasingly turnkey solutions, but they also are involved in development at imec to evaluate different material combinations and process scenarios. “Having access to EUV through imec is critical because customers are definitely addressing some hard problems, and they have to do multiple approaches at the same time because they’re not necessarily sure what’s going to be the final best solution,” added Wilbur.
When it comes to extending 193nm lithography processes, Wilbur pointed to the industry’s use of CVD hard masks, which require an underlayer that can be easily removed by wet clean once the pattern is etched. “For CVD hard-mask or multi-patterning schemes, customers need a material that can withstand going back through the litho and etch process multiple times,” said Wilbur.
Once the EUV capability is up and running, it will undergo double patterning and quadruple patterning methods needed to extend feature resolution even further below 20nm. After that comes high-NA EUV, sometime in the 2025 to 2027 timeframe, in which the numerical aperture jumps from 0.33 to 0.55.
“High-NA EUV uses 8X by 4X magnification masks. Instead of the dimensions of features on the mask being 4X in both dimensions, as we had been for 30 years, one of the dimensions will be going to 8X,” explained Aki Fujimura, CEO of D2S. “In order to keep the mask infrastructure compatible, high-NA masks are the same size as the other masks, 100 x 100mm, but it exposes a 12.5 x 25mm area on the wafer. This means you need two high NA masks to expose one layer. What’s a square on the mask will become a 1:2 aspect ratio rectangle on the wafer.”
Fig. 1: Milestones on the roadmap include nanosheet transistors in 2024 and CFETs in 2032. Metal pitch could baseline at 12-16nm. Source: imec
Continued advancement in fabrication methods and technologies will be essential to enable and further scale the next-generation of gate-all-around (GAA) transistors, DRAM architectures, and 3D NAND devices that today contain more than 200 layers.
While logic pushes the most advanced transistor structures, 3D NAND is the technology driver for many etch and fill processes. “Some of the most profound challenges in the semiconductor industry can be found in these etch applications, and scaling means they will become even more difficult. In production, this means etching features to a depth of multiple microns, while perfectly matching the result across the wafer on billions of these features,” said Lam’s Finch. “Critical etch capabilities required advanced uniformity and etch profile control, which is managed by the company’s data intelligence platform. The etchers can self-adapt to minimize process variations and maximize wafer output.
Transistors in 3D
Imec’s roadmap calls for implementing gate-all-around FETs (nanosheet transistors) in 2024, followed by forksheet FETs in 2028, and CFETs possibly in 2032 (see figure 1). “The transition from fins to nanosheets is part evolution and part revolution,” said TEL’s Clark. “Of course, the channel body thickness is now horizontal rather than vertical, so the channel width can be adjusted lithographically. That is advantageous for design, and means when we etch the fins to make nanosheets they can actually have a lower aspect ratio than a (multi-fin) finFET with similar effective channel width. And even though we still need vertical fin etches, the etch is no longer creating a body thickness and therefore, threshold voltage variation. But we do need to deal with etching through multiple Si and SiGe epi layers, which is new.”
While this is an evolutionary step, it’s non-trivial. “We can continue to make use of self-aligned source/drain and gate contacts in process flows that are very similar to what is used for finFETs, although the hard-mask and capping layers may need to become more robust to accommodate the additional etching needed for inner spacers and other processes,” Clark said. “The nanosheet structure also requires some new process modules including channel release, inner spacer etch and formation, bottom isolation, and much more challenging selective epi growth for source/drain and channels.”
But these refinements are not the whole story. As with all technology transitions, the scaling aspects make things harder for process engineers. “We still need to scale contacted gate pitch as well, so we will be challenged to fit gate stacks within the RMG (replacement metal gate) structure and attain multiple workfunctions. As a result, current research includes using dipole layers either in place of, or in addition to, workfunction metals in order to fit the gate stack into the RMG nanosheet volume,” said Clark.
Once the transistor structures are formed, the contact metal, with a focus on low resistance, must connect to a smaller source and drain surface. “Source and drain silicide volume needs to be controlled while reducing Schottky barrier height to lower contact resistance even further going forward,” he said.
The next step is still technically a gate-all-around device, called a forksheet FET, because there is a dielectric wall between the N and P sheets that look like protruding forks. The dielectric wall needs to be dense as it will be used for self-alignment and act as a hard mask, too, according to Clark. “That layer poses a number of challenges because it needs to be void-free, and it needs to stand up to etch, CMP, etc. required for patterning. Selective depositions could offer some big advantages going forward, both in terms of enabling more bottom-up approaches to self-alignment, and by enabling functional layers to be deposited only where needed and thereby save volume, in addition to buying back some process window.”
After forksheet transistors, the industry will transition to CFETs, when the n and pFET are stacked one on top of the other. Some leading chipmakers have begun work on these structures.
The number of changes that are in the works is mind-boggling. While Moore’s Law scaling continues to be relevant and necessary, it’s just one piece of a massive industry-wide innovation that is reaching into every facet of chip design through manufacturing, and even into the field. Chips are becoming more necessary, more diverse, and more reliable. And they also will need to talk to each other much more than in the past.
[Stay tuned for part two of this report next week, which will examine the revolution in interconnects and heterogeneous packaging.]