Semiconductor

Security Research: Technical Paper Round-up

Industry Research HW-related security papers at the USENIX Security Symposium include remote direct memory introspection, side channel attacks, transient execution attacks, physical removal on LiDAR, HW-assisted malware analysis, microarchitectural leakage. A number of hardware security-related technical papers were presented at the August 2023 USENIX Security Symposium. Here are some highlights with associated links. Technical Paper Research Organizations Remote Direct Memory

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Chip Industry’s Technical Paper Roundup: May 23

Industry Research Edge with RISC-V and HW accelerators; RL-guided routing; memory mapping using DL; cross-shape reconfigurable FET; memory disaggregation; EV charging security issues; PCM for analog in-memory computing; non-traditional design of dynamic logic using FDSOI; semiconductor optical amplifiers in data centers. New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations EigenEdge: Real-Time Software Execution at the Edge

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RL-Guided Detailed Routing Framework for Advanced Custom Circuits

A technical paper titled “Reinforcement Learning Guided Detailed Routing for Custom Circuits” was published by researchers at UT Austin, Princeton University, and NVIDIA. “This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. Comprehensive post-layout analyses based on industrial designs demonstrate

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Chip Industry’s Technical Paper Roundup: Mar. 28

Industry Research GAA FETs; thermal simulation in 3D-IC; zero trust environments; silicon photonics MEMS; semi-metals for interconnects; logic locking at the RTL; mechanical overtone frequency combs; photonics: GaSb/SiN tunable hybrid integrated laser; domain wall-magnetic tunnel junction analog content addressable memory. New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM

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Semiconductor

Chip Industry’s Technical Paper Roundup: Mar. 6

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Semiconductor

Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM

A new technical paper titled “NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems” was published (preprint) by researchers at UC San Diego, UT Austin, and Purdue University. Abstract“We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as implemented by the Intel Optane DIMM and reveal several of its

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Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning

A new technical paper titled “APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning” was published by researchers at UT Austin and Analog Devices. Abstract“Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated solutions for sizing has attracted

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Modeling and Thermal Analysis of 3DIC

A new technical paper titled “Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers” was published by researchers at UT Arlington. “This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent layers,” states the paper. Find the technical

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