Semiconductor

Chip Industry’s Technical Paper Roundup: August 22

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Semiconductor

EDA Tool To Detect SW-HW Vulnerabilities Ensuring Data Confidentiality In A RISC-V Architecture

A technical paper titled “SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors” was published by researchers at RWTH Aachen University, Robert Bosch, and Newcastle University. Abstract: “Despite its ever-increasing impact, security is not considered as a design objective in commercial electronic design automation (EDA) tools. This results in vulnerabilities being overlooked during the software-hardware design process. Specifically, vulnerabilities that allow

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Semiconductor

Overview Of The State Of Semiconducting Transition Metal Dichalcogenides (TMDC) Research

A technical paper titled “Potential of Transition Metal Dichalcogenide Transistors for Flexible Electronics Applications” was published by researchers at Advanced Microelectronic Center Aachen (AMICA), RWTH Aachen University, and Bergische Universität Wuppertal. Abstract: “Semiconducting transition metal dichalcogenides (TMDC) are 2D materials, combining good charge carrier mobility, ultimate dimension down-scalability, and low-temperature integration. These properties make TMDCs interesting for flexible electronics, where

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Research Bits: May 16

Germanium-tin transistor Scientists at Forschungszentrum Jülich, CEA-Leti, University of Leeds, Leibniz Institute for High Performance Microelectronics, and RWTH Aachen University fabricated a new type of transistor from a germanium-tin alloy. Charge carriers can move faster in the material than in silicon or germanium, which enables lower voltages in operation. “The germanium–tin system we have been testing makes it possible to

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Chip Industry’s Technical Paper Roundup: May 8

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Semiconductor

Hexagonal Boron Nitride Memristors With Nickel Electrodes: Current Conduction Mechanisms & Resistive Switching Behavior (RWTH Aachen)

A new technical paper titled “Resistive Switching and Current Conduction Mechanisms in Hexagonal Boron Nitride Threshold Memristors with Nickel Electrodes” was published by researchers at RWTH Aachen University and Peter Gruenberg Institute. Abstract: “The 2D insulating material hexagonal boron nitride (h-BN) has attracted much attention as the active medium in memristive devices due to its favorable physical properties, among others,

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Chip Industry’s Technical Paper Roundup: May 2

Industry Research Schottky barrier transistor; HW-accelerated RTL simulation; RISC-V microcontroller; GaN power devices; charging infrastructure and grid integration for electromobility; IFA for computing-in-memory; RISC-V vector HW for HPC; HW IP assurance against trojan attacks with ML. New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations The Schottky barrier transistor in emerging electronic devices THM University of

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Information flow policies for NVM Technologies

A new technical paper titled “Automated Information Flow Analysis for Integrated Computing-in-Memory Modules” was published by researchers at RWTH Aachen University. Abstract:“Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computing-in-memory (CIM). Various computer architectures have been proposed to integrate CIM blocks in their design, forming a mixed-signal

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Semiconductor

Optimizing The Growth And Transfer Process of Graphene (Cambridge, RWTH Aachen)

A technical paper titled “Putting High-Index Cu on the Map for High-Yield, Dry-Transferred CVD Graphene” was published by researchers at University of Cambridge, RWTH Aachen University, and National Institute for Materials Science. Abstract: “Reliable, clean transfer and interfacing of 2D material layers are technologically as important as their growth. Bringing both together remains a challenge due to the vast, interconnected

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Semiconductor

Vertical Nanowire Gate-All-Around FETs based on the GeSn-Material System Grown on Si

A new technical paper titled “Vertical GeSn nanowire MOSFETs for CMOS beyond silicon” was published by researchers at Peter Grünberg Institute 9, JARA, RWTH Aachen University, CEA, LETI, University of Grenoble Alpes, University of Leeds, and IHP. “Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased

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Looking Forward To SPIE, And Beyond

On the eve of this year’s SPIE Advanced Lithography + Patterning conference, I took a look at the IEEE Devices and Systems Roadmap’s lithography section. It’s especially notable for the emergence of EUV lithography, which has quickly become critical for advanced logic. High-NA tools to support still smaller dimensions are on the horizon. In the near-term, though, the key challenge

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