Semiconductor

Curvilinear Mask Patterning For Maximizing Lithography Entitlement

Manufacturing, Packaging & Materials WHITEPAPERS Practical solutions to overcome the computational challenges associated with this technique, as well as the difficulties of manufacturing curvilinear masks. Curvilinear Mask Patterning is a cutting-edge lithography technique that promises to maximize lithography entitlement by addressing complex design challenges and critical yield limiters. However, its widespread deployment has been limited by significant computational challenges. This

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Semiconductor

Patterning With EUV Lithography Without Photoresists

A technical paper titled “Resistless EUV lithography: photon-induced oxide patterning on silicon” was published by researchers at Paul Scherrer Institute, University College London, ETH Zürich, and EPFL. Abstract: “In this work, we show the feasibility of extreme ultraviolet (EUV) patterning on an HF-treated Si(100) surface in the absence of a photoresist. EUV lithography is the leading lithography technique in semiconductor

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Semiconductor

High-NA EUV Progress And Problems

High-NA EUV will enable logic scaling for at least the next couple process nodes. It’s complex, expensive, and a feat of optical engineering, but there are a lot of components with mixed progress. Harry Levinson, principal lithographer at HJL Lithography, talks  about when this technology will likely show up, what problems still need to be resolved, and what comes next.

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193i Lithography Takes Center Stage…Again

Cutting-edge lithography to create smaller features increasingly is being supplemented by improvements in lithography for mature process nodes, both of which are required as SoCs and complex chips are decomposed and integrated into advanced packages. Until the 7nm era, the primary goal of leading-edge chipmakers was to pack everything onto a single system-on-chip (SoC) using the same process technology. Since

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Semiconductor

EUV Lithography: Results of Single Particle Volume Charging Processes in EUV Exposure Environment With Focus On Afterglow Effects

A new technical paper titled “Particle charging during pulsed EUV exposures with afterglow effect” was published by researchers at ASML, ISTEQ B.V., and Eindhoven University of Technology. Abstract“The nanoparticle charging processes along with background spatial-temporal plasma profile have been investigated with 3DPIC simulation in a pulsed EUV exposure environment. It is found that the particle charge polarity (positive or negative)

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Semiconductor

Big Changes Ahead In Power Delivery, Materials, And Interconnects

Part one of this forecast looked at evolving transistor architectures and lithography platforms. This report examines revolutions in interconnects and packaging. When it comes to device interconnects, it’s hard to beat copper. Its low resistivity and high reliability have served the industry exceedingly well as both on-chip interconnect and wires between chips. But in logic chips, with interconnect stacks rising

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Large-Scale Nanometer-Thick Graphite Film (NGF) As A EUV Pellicle

A new technical paper titled “Graphite Pellicle: Physical Shield for Next-Generation EUV Lithography Technology” was published by researchers at University of Ottawa, Sungkyunkwan University, and Hanbat National University. Abstract “Extreme ultraviolet lithography (EUVL) is widely employed in the electronics, automotive, military, and AI computing areas for IC chip fabrication. A pellicle is a thin and transparent membrane that protects a

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Semiconductor

Tech Forecast: Fab Processes To Watch Through 2040

The massive proliferation of semiconductors in more markets, and more applications within those markets, is expected to propel the industry to more than $1 trillion by 2030. But over the next 17 years, semiconductors will reach well beyond the numbers, changing the way people work, how they communicate, and how they measure and monitor their health and well-being. Chips will

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More Accurate And Detailed Analysis of Semiconductor Defects In SEM Images Using SEMI-PointRend

A technical paper titled “SEMI-PointRend: Improved Semiconductor Wafer Defect Classification and Segmentation as Rendering” was published (preprint) by researchers at imec, University of Ulsan, and KU Leuven. Abstract:“In this study, we applied the PointRend (Point-based Rendering) method to semiconductor defect segmentation. PointRend is an iterative segmentation algorithm inspired by image rendering in computer graphics, a new image segmentation method that

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Semiconductor

Process Innovations Enabling Next-Gen SoCs and Memories

Achieving improvements in performance in advanced SoCs and packages — those used in mobile applications, data centers, and AI — will require complex and potentially costly changes in architectures, materials, and core manufacturing processes. Among the options under consideration are new compute architectures, different materials, including thinner barrier layers and those with higher thermal budgets, as well as higher aspect-ratio

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Measuring 3D Sidewall Topography & LER for Photoresist Patterns Using Tip-Tilting AFM Technology

A new technical paper titled “Enhancing the precision of 3D sidewall measurements of photoresist using atomic force microscopy with a tip-tilting technique” by researchers at National Metrology Institute of Japan (NMIJ) and National Institute of Advanced Industrial Science and Technology (AIST). “We have developed a technique for measuring the sidewall of the resist pattern using atomic force microscopy (AFM) that

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Semiconductor

Devices And Transistors For The Next 75 Years

The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers,

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IOT

Using Electron Beams to Draw Tiny Shapes onto Silicon

Over the past few years we’ve seen several impressive projects where people try to manufacture integrated circuits using hobbyist tools. One of the most complex parts of this process is lithography: the step in which shapes are drawn onto a silicon wafer. There are several ways to do this, all of them rather complicated, but [Zachary Tong] over at Breaking

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