Using visually lossless video compression to cut the number of MIPI transport lanes required for displays.

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By Joseph Rodriguez and Simon Bussières

It is hard to believe, but it has been 20 years since MIPI Alliance was first founded. The organization was originally formed to standardize the video interface technologies for cameras and displays in phones, with the MIPI acronym standing for Mobile Industry Processor Interface (MIPI). As the mobile industry has evolved, MIPI Alliance has evolved with it. MIPI is now a name, not an acronym, and the scope of the organization has expanded considerably. MIPI specifications now cover physical layer, multimedia, chip-to-chip, control/data, and debug/trace and software.

The first iteration of the MIPI Display Serial Interface (DSI) specification was released in 2006. The specification, which defines the interface between processors and displays, achieved widespread adoption. MIPI DSI-2 is now the current version of the standard and is the leading display interface for mobile phones and tablets. In recent years, as mobiles have influenced display trends in other markets, DSI-2 is now also commonly used in augmented and virtual reality (AR/VR) applications, as well as the automotive industry for displays in ADAS (advanced driver assistance systems) and infotainment systems.

MIPI DSI-2 supports two video compression codecs from VESA (Video Electronics Standards Association): VESA DSC and VDC-M. VESA Display Stream Compression (DSC), released in 2014, was the industry’s first visually lossless video compression codec. DSC emerged in response to the need for an industry standard for video compression on display interfaces and provided designers with a way to support increasing bandwidth requirements, without compromising on cost, power consumption, and, most importantly, visual quality. As display bandwidth requirements kept growing, VESA identified the need for a second compression codec that would offer additional compression capabilities. VDC-M (VESA Display Compression) was announced in 2018 and MIPI Alliance was the first organization to adopt VDC-M into MIPI DSI-2.

DSC and VDC-M are both visually lossless. This means that an end user cannot distinguish between the uncompressed original images and the compressed version. This has been proven through a series of rigorous tests conducted by VESA. Since the codecs are used across a wide range of applications, the algorithms have been designed to render excellent quality across all types of content.

Let’s dive a little deeper into some of the design advantages associated with using VESA video compression with the MIPI DSI-2 interface.

VESA DSC can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image. By implementing VESA DSC, designers can typically cut the number of MIPI transport lanes in half, which translates to savings in power, area, and design complexity. For example, a mobile High Dynamic Range (HDR) display running at 4K / 60 frames per second (fps) / 30 bpp requires 16.5 Gbit/s (uncompressed) of bandwidth. To transmit the video over a MIPI DSI-2 link, using a MIPI D-PHY, 8 lanes running at 2.1Gbit/sec would be required. To support 8 lanes requires two instances of the DSI-2 controller and D-PHY. With VESA DSC, visually lossless compressed video can be transmitted using only 4.4 Gbit/s of bandwidth. The MIPI link can use one instance of 4 lanes at 1.1 Gbit/s. This lane rate reduction from 2.1 Gbit/s to 1.1 Gbit/s comes with a significant drop in the DSI controller clock rate from 525 MHz to a much more manageable 275 MHz.

VDC-M uses a set of even more sophisticated video encoding tools to achieve yet higher compression factors, all while offering the same or even better picture quality. For example, it can reduce a 30 bpp uncompressed image to 6 bpp, and in some use cases, it can be visually lossless at a 6X compression ratio. An AR headset with two displays of 5K x 5K at 120 fps / 30 bpp requires 100 Gbit/s (uncompressed) bandwidth per eye. Transmitting such high bandwidth video over a MIPI DSI-2 link, even when using the latest C-PHY or D-PHY standard versions, is challenging in terms of cost, power, and potential problems with EMI. With VDC-M, visually lossless compressed video can be transmitted using only 20 Gbit/s of bandwidth per eye. To transmit 20 Gbit/s the MIPI link can use a D-PHY with 4 lanes at 5 Gbit/s or C-PHY with 3 lanes/trios at 2.9 Gsym/s.

Rambus MIPI DSI-2, VESA DSC, VDC-M IP solutions help designers manage the bandwidth requirements of next-generation displays with extremely high resolutions and fast refresh rates. Combining both MIPI DSI and VESA video compression expertise, the IP cores are optimized for maximum performance and offer a mature IP solution to speed up the product development cycle and lower design risk. For more information, visit the Rambus VESA video compression and MIPI DSI-2 webpages.

Simon Bussières is director of systems architecture, Interconnect Designs at Rambus.

Joseph Rodriguez

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Joseph Rodriguez is a senior product marketing engineer for IP cores at Rambus.

Source: https://semiengineering.com/mipi-dsi-2-vesa-video-compression-enable-next-generation-displays/