Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade.

An IP data library consists of many views and formats, which must be correct and consistent to ensure correct IP integration. In addition, with each IP revision, it is important to ensure that there are no unexpected changes. Design IP blocks go through many revisions, PDK changes and post release updates. As the IP’s development cycle progresses, unexpected and incorrect changes in newer versions of the IP may lead to costly roll backs or re-spins.

Fig. 1: Version-to-version IP QA involves multiple design views and formats.

In this article, we discuss the importance of having a robust version-to-version IP QA methodology in IP production and integration flows, as well as its impact on the final quality of silicon.

IP revision challenges

IP data contains several views and formats, which must be validated for unexpected changes with each new revision. This presents the following challenges.

Keeping track of changes between versions

Identifying overall version changes requires analyzing the changes that occur within each format. This is a manually intensive process that must be repeated over many versions and revisions. Since IP blocks go through multiple revisions, it is essential to have a repeatable process to keep track of all the changes.

Unexpected changes between versions

With every IP revision, there will be changes from the previous revision. However, these are expected changes. If there are unexpected changes, they can pass through the flow uncaught and cause problems much later in the flow.

Spec changes with each revision

For each revision made to the design IP, performance and specs may change either intentionally (e.g., targeted overall power improvement of the IP), or as a side effect of changes (e.g., timing or power differences from layout modifications).

Lack of industry standard IP QA solution for IP version QA

In-house solutions to solve this challenge can be difficult to build and maintain. These solutions must keep up with the latest standards and hence need to be constantly updated. In-house tools may also require dedicated resources for development and maintenance. Additionally, they must be scalable and cater to all IP blocks irrespective of type or process technology.

Impacts of incomplete QA between IP versions

Ineffective version-to-version IP validation can lead to several issues. For one, it can slow down the development process, as the validation process takes longer to complete. This can lead to delays in delivering the newer version of the IP on schedule. Additionally, it can lead to increased costs, as more resources are required to perform the validation.

Another issue that can arise from ineffective version-to-version IP validation is an increase in the number of bugs or errors in the final product. This is because the validation process may not catch all issues or may not be thorough enough to identify all potential problems. As a result, users may experience quality issues that could have been avoided if the validation process had been more efficient. Furthermore, integration into a larger SoC can be challenging, as the IP may end up with sub optimal PPA (performance, power, and area) metrics thereby affecting the final quality of silicon.

Requirements of a robust IP version-to-version QA methodology

A good approach to solve the above-mentioned challenges and its impacts is to have a scalable, repeatable, and comprehensive solution to compare different IP revisions, identify unexpected changes, and ensure a high-quality revision at every iteration.

The IP version-to-version QA methodology should be tool agnostic, support all design types and include a supporting framework for reporting, debugging, and viewing results for faster design closure. A complete solution may include a comparison engine that compares each format present in the older and newer version of the IP and report the differences in a user-friendly manner. The expected mismatches between the two versions can be waived, and the unexpected mismatches should be fixed in the IP data. This ensures that IP integration teams obtain the correct information to make design decisions when using the newer version of the IP.

Fig. 2: A scalable, repeatable version-to-version QA framework.

The comparison engine can be used to find and report several differences – such as format comparisons, PPA score differences, changes in the layout and other version-to-version checks – between the two IP versions.

Table 1: Types of version-to-version comparisons critical to IP development.

Summary

IP blocks are an essential component for today’s complex SoCs. The quality of the IP must be validated before integration to ensure there are no surprises later in the flow. As these IP blocks go through multiple revisions, it is necessary to keep track of the changes that go into them. Unexpected differences between versions can cause severe issues during integration thereby affecting the final quality of silicon.

These impacts can be mitigated with a scalable, repeatable, and comprehensive methodology that includes a robust comparison engine, supporting framework for user-friendly reporting, and easy analysis of differences.

This will ensure a high-quality revision of the IP at every iteration.

Source: https://semiengineering.com/importance-of-qualifying-ip-revisions/