Disruptions to the global semiconductor supply chain caused by the COVID-19 pandemic had a severe impact in nearly every sector of the worldwide economy, and especially the worldwide semiconductor market. Due to a shortage of chips, the global auto industry alone suffered a $210 billion loss in 2021, accompanied by a 7.7 million unit production drop, according to AlixPartners, a global consulting firm.
The United States was particularly hard hit by the chip shortage, with Intel estimating that it cost the U.S. economy $240 billion. “Semiconductors power nearly every new computer, smartphone, car, and the cloud servers that underpin the world economy — and even the internet itself — as well as the advanced technologies and weapons systems critical for the national defense,” says the U.S. Department of Commerce. “However, the vast majority of semiconductor production, including all production of advanced, or ‘leading-edge’ semiconductors, occurs overseas by a limited number of foreign producers.”
Over the past two decades, the U.S. share of worldwide semiconductor manufacturing declined to 12%, a substantial decrease from the 37% share the country held in 1990, according to the Semiconductor Industry Association (SIA). Likewise, Europe’s chip production dropped to 8% of global capacity from 25% in 2000, according to A.T. Kearney. In both cases this is due, in part, to substantial subsidies offered by foreign governments over those two decades to lure manufacturers to their shores, placing the one-time market leaders at a competitive disadvantage.
To address this decline, the U.S. government passed the CHIPS and Science Act in August 2022 for the revitalization of semiconductor manufacturing within its borders, allocating some $280 billion in new funding over a decade. The legislation includes $53 billion for semiconductor manufacturing and research and development, along with $24 billion in tax credits to incentivize chip production and drive additional private investments in U.S.-based manufacturing facilities. Companies like GlobalFoundries, Intel, Micron, and Samsung already have committed $260 billion toward new and expanded facilities in the United States, according to McKinsey.
Likewise, the European Commission reached agreement on the European Chips Act in April, approving €43 billion ($47 billion) in public and private investments, with a goal of increasing the EU’s chip capacity to 20% by 2030. And there are similar efforts underway in Japan and Korea.
While all of these investments in semiconductor manufacturing promise to bolster the supply of chips, building complex new facilities required for the next generations of manufacturing technology also poses significant challenges. There is a need for extensive research and development to address critical areas in achieving high-volume manufacturing (HVM) for the advanced process technologies these fabs will incorporate.
One such critical research area, particularly for the U.S., is metrology, where there is a growing need for robust new techniques to accurately measure and characterize the novel materials and structures of increasingly complex chips. “There is a need to keep pushing metrology research investments because that is where you gain yield,” says Samuel Lesko, senior director and general manager at Bruker Nano Surfaces & Metrology. “You can’t really produce without metrology.”
Recognizing the importance of addressing these challenges, the U.S. CHIPS R&D Metrology Program, administered by the National Institute of Standards and Technology (NIST), published “Metrology Gaps in the Semiconductor Ecosystem” on June 5th.  This document serves as a strategic roadmap for metrology research and development. It combines two years of research, strategic planning, organizational development, and stakeholder engagement to identify 10 priority areas under 7 grand challenges, with an additional 32 “Path Forward” elements that provide technical roadmaps to overcome those challenges.
Fig. 1: The Metrology Gaps roadmap highlights the most pressing needs for precise, accurate measurements. Source: NIST
“The inclusion of this program within the CHIPS Act is a recognition that innovation in the semiconductor ecosystem requires test and measurement technology to advance at the same pace,” says Charles Schroeder, a National Instruments fellow. “We believe the deep technology and business insight that comes from test data is key to enabling a thriving semiconductor ecosystem, and as such we recommended that test and measurement be a priority R&D category to drive innovation in the semiconductor ecosystem and scalability to production-ready technology.”
Others agree. “It’s good to have a framework where everybody’s aligned and knows what manufacturers care about,” says David Fromm, head of engineering at Promex Industries. “This publication helps us all see where the challenges are, and that’s how we get good focus and good innovation.”
Synthesizing R&D Priorities
To develop this publication, NIST sponsored two metrology workshops with industry experts and researchers to understand the technology gaps affecting U.S. semiconductor manufacturing capabilities. An internal group of subject matter experts was formed to review stakeholder input and metrology needs, and statistical analyses were performed to identify and prioritize the metrology R&D gaps.
The CHIPS R&D Metrology Program then conducted meta-analyses of existing industry roadmaps published by the IEEE — the Heterogenous Integration Roadmap and the International Roadmap for Devices and Systems (IRDS). The two roadmaps corroborated the Metrology Gaps publication’s grand challenges and focus areas to meet both short- and long-term metrology needs.
The Metrology Gaps in the Semiconductor Ecosystem publication serves a dual purpose under the CHIPS Act. It provides a technical roadmap to help direct metrology companies toward solutions for future needs, while also providing a structure for CHIPS Act funding to help ensure investments are being directed into areas of the most critical need, and that all future needs are being addressed. “This publication serves as a resource for stakeholders interested in learning more about the CHIPS R&D Metrology Program and will be used as a tool to assist future program decision-making and R&D investment allocation. It is formal documentation of the NIST process.”
The metrology industry is constantly evolving to keep pace with the test and measurement needs of the next node. However, rapidly changing processes, new materials, chiplets, SoCs, and advanced packaging are creating broad new challenges for metrology. While the Metrology Gaps publication includes these issues in three of its grand challenges for future needs, many companies are already pursuing solutions to all of them:
- Grand Challenge 2: Advanced Metrology for Future Microelectronics Manufacturing.
- Grand Challenge 3: Enabling Metrology for Integrating Components in Advanced Packaging.
- Grand Challenge 4: Modeling and Simulating Semiconductor Materials, Designs, and Components.
“We’re not waiting for the CHIPS Act to level the priorities,” says Lesko. “We are already in direct contact with our tier-one customers across the boards, and we are closely working with them to meet these needs now. The Metrology Gaps document helps confirm that we are on the right track.”
One key element of the R&D Metrology Program is the requirement for recipient organizations to make their research findings and results publicly available. “Outcomes of the CHIPS R&D Metrology Program will include data, measurement methods, reference process design kits, reference materials, standards, publications, and related digital products,” according to NIST. “The CHIPS R&D Metrology Program will establish a digital exchange ecosystem to provide stakeholders with access to CHIPS metrology research results.”
This emphasis on open access is designed to remove barriers to key developments. This approach creates a fertile ground for collaboration and innovation, as it allows different stakeholders to build upon existing knowledge, refine methodologies, and explore new avenues of research. This collaborative approach also helps break down the intellectual property silos, enabling cross-pollination of ideas and fostering an environment of innovation.
“It can open up thought from a wider range of backgrounds, and that diversity and thinking can lead to breakthroughs,” says Fromm. “Because what may not be obvious to me might be obvious to you. So, that’s a potentially good thing.”
Inevitably, however, the commoditization of technology fosters consolidation within the industry. As more organizations gain access to shared knowledge and build upon it, the barriers to entry become higher for new players. Established companies, possessing a wealth of expertise and resources, are better positioned to capitalize on the shared research, further expanding their influence and market share.
This consolidation, driven by a collective effort to advance the state of the art, usually leads to the emergence of dominant players and a more streamlined industry structure. Not everyone sees this as a negative outcome, however, because there still will be areas of value-add beyond IP differentiation where testing and metrology companies can succeed.
“NI believes that a holistic rethinking of the supply-chain and the ability to streamline the engineering to production flow will provide the U.S. semiconductor supply-chain with a competitive advantage,” says Schroeder. “As such, we are innovating in four areas:
- The development of tools and capabilities that embrace shift-left and digital engineering mindsets that leverage software and virtualization technology along with measurements and metrology to significantly improve the time-to-market of new semiconductor capabilities.
- The development of smart, connected test systems that speed the time from measurements to insight and lower the operating costs of semiconductor companies.
- The development of hyper-automated, advanced data analytics that allow semiconductor companies to get product and business transforming insight from their test and measurement data.
- The development of connected software tools that allow engineers from across semiconductor companies to collaborate on the development of next generation test systems.”
As semiconductor components reach nanoscale dimensions, traditional metrology methods struggle to accurately measure critical parameters such as linewidths, stochastics, gaps, holes, and bonding and bump pitch. Achieving accurate measurements at nanometer levels is also vital for understanding the thickness and composition of semiconductor layers. Deviations of even a few nanometers can significantly impact the performance of devices, making sensitivity and accuracy key factors in metrology. Enhancing the sensitivity of measurement tools to capture small signals will allow for more precise control of device properties and performance.
“The rate of change and innovation in the semiconductor industry is enormous and inspiring,” says NI’s Schroeder. “New technologies are being developed every day, and the landscape is constantly changing. These developments will trigger new challenges and metrology needs. For example, the research into the use of the sub-THz frequency bands in the 6G cellular standard will surface the need for new packaging, interconnect, metrology and calibration, and cost-effective test and measurement equipment.”
In addition to individual device measurements, there is a growing need for metrology techniques that can accurately characterize complex three-dimensional designs, which often involve multiple materials with different coefficients of thermal expansion. This makes compatibility and reliability crucial factors. Currently, methodologies for simulating and characterizing these complex structures are not widely available, hindering the efficient design and manufacturing of semiconductor devices. Developing accessible and comprehensive methodologies to address this gap will be instrumental in advancing complex assembly characterization.
“With the new multi-die solutions and heterogenous ICs, there might be a mechanical element, an optical element, or other element that makes it really complex, but these different materials all have to be compatible throughout the processing,” says Fromm. “We might know where the risk lies in a design, but until you start building it, you don’t really know where the faults or errors might be, and that’s hard to determine. Those methodologies are not widely available right now.”
Nanosheet technology, with its low aspect ratios and nanometer-scale dimensions, also poses unique measurement challenges. Techniques such as X-ray and ellipsometry are being explored by companies like Bruker to achieve the necessary resolutions for accurately characterizing these devices. However, the iterative nature of the metrology process requires ready sampling to quantify the capabilities of these measurement tools effectively. While there is a range of available technology, the development and validation of precise measurement techniques remain crucial.
“I’m not sure we can call it a ‘Metrology Gap’ because we do have technology available,” says Lesko. “Some solutions still need to be confirmed, especially for the nanosheet, which is very challenging. But we have multiple technologies that may apply here. The signal is very small, so it’s all about sensitivity. We are very hopeful to be able to address these needs with existing systems rather than going after new developments.”
One key to improved yields and output in semiconductor manufacturing is identifying and addressing failures and root causes efficiently. Inline processing and direct measurements offer significant advantages in this regard. By enabling real-time observation and analysis during the fabrication process, inline metrology can save time and resources by preventing costly deviations and allowing prompt adjustments. But that reality is still far off.
“Where we are now is pretty arcane and kind of the stone age of metrology,” says Fromm. “We’re really just tearing things apart to see what broke. If we build a device and something doesn’t work, we’re typically stuck with destructive testing, and even those methods are somewhat unsatisfying. When you build something to the end and you have to unwind it, that takes a lot of time and you can spend a lot of time going down the wrong path. If you can get direct measurements during production, you don’t waste as much time. Inline processing is sort of the holy grail of metrology right now, and we’re not there yet, but the Metrology Gaps publication from NIST can help us get there, especially with companies sharing their research and development.”
These issues are only getting more complex at each new process technology. “For every node descent, the need for sampling goes up. We need to sample more,” says Chris Mack, CEO of Fractilia. “There’s definitely a desire to have full wafer coverage of every die in HVM for defect measurements using e-beam, but the throughput is not yet high enough to handle that. You need more current, more electrons, a larger field-of-view, and faster scanning. You need faster stages that move, and you need multiple beams, and people are pursuing all of those things simultaneously. Resolution is shrinking very slowly, though, while feature sizes are shrinking very quickly, and we’re reaching a crossing point where this is seriously problematic.”
The challenges faced by the semiconductor industry, particularly during recent global events like the pandemic, have brought increased awareness to the criticality of semiconductor manufacturing. From hardware fabrication to wafer fabrication and packaging, more people are expressing interest in solving the industry’s challenges. An influx of talent and renewed focus could lead to a renaissance in domestic and regional semiconductor ecosystems, bolstering innovation and driving growth.
“At the very least, the CHIPS Act is bringing awareness to people who never really thought about where their hardware comes from, and the pandemic really illustrated this,” says Promex’s Fromm. “The more people are aware of these problems, the more they become interested in solving them. People who might have gone into software or some other aspect of technology, might choose to work with semiconductors at the wafer fabrication level, or work in packaging. Interest in these fields has waned over the past decade, so one of the good things that might come out of the chip shortage is more people deciding to do this work, and that can never be bad. In fact, if that’s the only good thing that comes out of it, that will help significantly.”
To address the future metrology needs of the semiconductor industry, collaboration between industry players, academic institutions, and government agencies is essential. NIST’s Metrology Gaps in the Semiconductor Ecosystem provides a roadmap for solving the metrology industry’s biggest problems, with specific guidelines for research and action. With the requirement that companies make their research and solutions in these areas publicly available, there is new hope that the metrology solutions needed for future generations of complex chips are achievable.
1. “Comments from CEO Pat Gelsinger and CFO Dave Zinsner,” April 28, 2022.
2. “Metrology Gaps in the Semiconductor Ecosystem,” NIST, June 5, 2023.